1. Field of the Invention
This invention relates to a layout data generation equipment and layout data generation method which realizes electro-migration in the process of generating layout data of a semiconductor integrated circuit. Further, this invention relates to a manufacturing method of a semiconductor device using this generated layout data.
2. Description of the Related Art
At the time when a large current flows through a metal wire of a semiconductor integrated circuit, a phenomenon called electro-migration, whereby a metal atom shifts, sometimes occurs.
That is, at the time when a current flows through a metal wire of a semiconductor integrated circuit, metal atoms receive a stress by a momentum exchange caused by a collision with flowing electrons and shift in the direction of the flow of the electrons. This phenomenon is known as electro-migration. When electro-migration occurs, the trails of the above stated metal atoms which shift in the direction of the flow of the electrons, become an atom void and these atom voids are accumulated in the upper flow of the electron flow. When a sufficient number of these atom voids have accumulated, the effective cross-section area of the metal wire is reduced and finally, the wire breaks, the electrical conduction of the wire is lost, the resistance of the wire increases and failures in signal transmission may occur.
In addition, the occurrence and progress of this electro-migration is influenced by a current near a unit cross section area (below referred to as current density of wiring) and atmosphere temperature. For example, the lifetime of a wire is assumed to be proportional to the square or the cube of the current density of the wire. Japanese Laid Open Document 1995-153845 is used as a reference.
This electro-migration is becoming one of the main causes of failure in a semiconductor device. Particularly, in the field of semiconductors whose development is progressing rapidly in recent years, the current density of a wire has increased considerably with miniaturization and thinning of the metal wire and the possibility of electro-migration occurring is increasing.
As a result, electro-migration should be prevented and in the design stage of a semiconductor integrated circuit, a realization of electro-migration verification in generated layout data and an improvement in the reliability of a semiconductor integrated circuit is being achieved.
Consequently, this invention aims to realize a reliable, high yield, highly integrated semiconductor integrated circuit by proposing a layout data generation equipment and layout data generation method with an improved accuracy of verification of electro-migration which is realized in the process of generating the layout data of a semiconductor integrated circuit in addition to a manufacturing method of a semiconductor device which uses layout data generated by this layout data generation equipment and generation method.